An integrated circuit (“IC”) is a device (e.g., semiconductor device) that includes many electronic components, such as transistors, resistors, diodes, etc. These electronic components can be connected together to form multiple circuit components such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.
Design engineers design an IC by transforming logical or circuit descriptions of the IC's components into geometric descriptions, called layouts. IC layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules.
To create layouts, design engineers often use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts. Examples of such tools include (1) standard cell libraries that provide numerous cells that can be instantiated as circuit modules in a design, (2) placement tools that define the location of the various circuit modules in a layout, (3) routing tools that define the wiring between the circuit modules, and (4) verification tools that verify that the designed layout will meet design operation requirements.
One type of verification tools are thermal analysis tools. Prior thermal analysis tools dealt mostly with the thermal properties of the IC packages and often ignored thermal properties on the IC. These prior tools were mainly concerned about the total power dissipation of the IC, and about whether a specific package was sufficient to cool a given IC. As a result, the IC often was treated as a lumped heat source, while the model for the package was very detailed, including details regarding airflow around the package.
In recent years, the emergence of multi-die IC designs has created a greater need for on-chip thermal analysis. Multi-die IC designs incorporate two or more dies (i.e., wafers) within a single integrated circuit (IC). Some benefits of multi-die IC designs include providing greater functionality in a smaller space and operating at faster speeds as the multiple dies are located within the same package and therefore suffer less propagation delay than two dies in two separate packages.
Logically, each die within a multi-die IC design may act as a different processing unit, digital signal processor (DSP), or system-on-a-chip (SoC) with each die being comprised of multiple circuit modules, interconnects, etc. Physically, these dies can be configured in several different arrangements (e.g., horizontal arrangement of dies or vertically stacked dies) within a single package. Each arrangement produces a different temperature distribution with each temperature distribution useful in determining the operational viability of the configuration within the real world.
Creating a functional multi-die design requires the design to not only successfully perform the operations specified in the design, but the design must also overcome the real world physical constraints that determine the viability of the design within the real world. One such physical constraint includes the heat constraint which if exceeded could result in a malfunction, electrical damage, or physical damage to the components (e.g., circuits) of the IC that implement the design.
Heat is byproduct of the current traversing the various circuits of the IC. A major contributor to the resulting heat generated by the design is the amount of leakage current. As illustrated in FIG. 1, leakage current is greatly affected by on-chip temperature variations. In fact, a circular dependency exists between the on-chip temperature, leakage current, and power dissipation. As illustrated in FIG. 2, the leakage current 210 affects the power dissipation 215. As the leakage current 210 rises, the power dissipation 215 also rises along with it. The power dissipation 215 increases the temperature 205, which in turn increases the leakage current 210. This circular set of dependencies creates the potential for a runaway feedback loop in which the temperature of the IC continually increases with the leakage current.
By producing on-chip thermal models for a multi-die IC design, layout designers will have additional means to overcome the heat constraint. Specifically, a multi-die IC design may satisfy or violate the heat constraint depending on how the different dies are configured within a particular package. As noted above, each configuration produces a different thermal signature. For instance, each die in a horizontally arranged die configuration may experience equal amounts of heat dissipation through the package thus producing a first thermal signature, whereas the same dies in a vertically stacked configuration will include some dies located further away from the package with the heat generated from these dies being more difficult to dissipate, thus producing a second thermal signature. Each such thermal signature can then be used to determine how cool and how fast a multi-die design is capable of operating. Additionally, accurate thermals signatures for multi-die designs identify thermal problems early in the design cycle. By being able to detect the thermal problems, layout designers will be able to select an optimal configuration and therefore better account for the heat constraint at design time.
Accordingly, there is a need to perform thermal analysis to model the thermal interaction between the multiple dies of a multi-die design. Moreover, there is a need to efficiently perform such multi-die thermal analysis. Such efficient analysis should reduce the amount of memory and processing resources that would otherwise be consumed when aggregating thermal models that were individually computed for each die of the multi-die IC design.